Detailed Description
To use these clock inputs, remove jumpers across AFX SEL headers J186 and J187.
Table 1-10:
Single-Ended SMA Clock Connections
FPGA Pin
AP33
R31
Net Name
CLK_1
CLK_2
SMA Connector
J171
J172
Differential SMA Global Clock Inputs
[ Figure 1-2 , callout 12 ]
The ML628 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA clock pins are
connected to the SMA connectors as shown in Table 1-11 .
Table 1-11:
Differential SMA Clock Connections
FPGA Pin
AN33
AP33
J33
H33
Net Name
CLK_DIFF_1_P
CLK_DIFF_1_N
CLK_DIFF_2_P
CLK_DIFF_2_N
SMA Connector
J167
J168
J169
J170
SuperClock-2 Module
[ Figure 1-2 , callout 13 ]
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise and low-jitter clock source for the ML628 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin. Table 1-12 shows the FPGA I/O mapping for the SuperClock-2
module interface. The ML628 board also supplies 5V, 3.3V, and 2.5V input power to the
clock module interface.
Table 1-12:
SuperClock-2 FPGA I/O Mapping
FPGA Pin
B35
B36
C12
C11
BC33
BD33
A23
A24
G26
Net Name
CM_LVDS1_P
CM_LVDS1_N
CM_LVDS2_P
CM_LVDS2_N
CM_LVDS3_P
CM_LVDS3_N
CM_GCLK_P
CM_GCLK_N
CM_CTRL_0
J32 Pin
1
3
9
11
17
19
25
27
61
ML628 Board User Guide
UG771 (v1.1) February 19, 2014
21
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